The Evolving Interconnect

By Ann Steffora Mutschler – Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways.

The basic concept behind cache is that data is stored closer to processor for faster access. Cache coherence allows copies of that data to be stored in multiple places. But to be coherent, it also has to be updated regularly at all places where it is stored, and that means the interconnects have to keep up with this whole process.

“So suddenly, instead of just talking to memory you’re talking to local memories, and those local memories are talking to other people’s local memories to try and make sure whenever you need something you’ve got the right version,” Drew Wingard, CTO at Sonics said. “That has a big impact on what happens at the interconnect fabric level on these chips.” more>

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